1. Field of the Invention
The present invention relates to a logic circuit test apparatus and a logic circuit test method for testing a logic circuit by generating original test signals from common test signal output terminals which are smaller in number than input terminals of the logic circuit and/or by generating expected signals from expected signal output terminals which are smaller in number than output terminals of the logic circuit.
2. Description of the Related Art
When a logic circuit (hereinafter referred to as “CUT” or “circuit under test”) is tested, input signals (hereinafter referred to as “input test pattern”) constituted by a predetermined set of logic signals for causing the logic circuit to operate in an intended manner are inputted to input terminals of the CUT from a logic circuit test apparatus (hereinafter referred to as “tester”). The CUT performs a predetermined operation according to the inputted test pattern, and outputs output signals from output terminals thereof as a result of the operation. Whether or not the CUT operates normally is determined by comparing the output signals of the CUT with expected signals (hereinafter referred to as “output test pattern”) which are to be outputted when the CUT is normal.
In the tester for testing the CUT, the number of terminals for outputting the input test pattern to the input terminals of the CUT and the number of terminals for receiving the output signals of the CUT for the comparison of the output signals of the CUT with the output test pattern should be greater than the number of the input terminals and the number of the output terminals of the CUT. That is, the test of the CUT cannot be performed if the number of the terminals of the tester is smaller than the number of the corresponding terminals of the CUT. To this end, the following method is proposed, which makes it possible to test the CUT even with the use of a tester having a reduced number of terminals.
An exemplary method for reduction of the number of the terminals of the tester for the input test pattern is to employ a random pattern generator including linear feedback shift resistors (LFSRs) for reducing the number of inputs from the tester. In this case, the input test pattern to be generated is a periodic pseudo-random pattern, failing to provide an input state suitable to detect a malfunction (or a defect). Therefore, the input test pattern often suffers from a lower malfunction detection ratio. Further, it is impossible to apply exactly the same input test pattern as an original input test pattern prepared for the test of the CUT, failing to ensure a test quality comparable to the original test pattern. That is, the malfunction detection ratio is generally reduced.
An exemplary method for reduction of the number of the terminals of the tester for the output test pattern is to add a compression circuit including a multiple input signature resister (MISR) for the reduction of the terminals. In this method, there is a fear that malfunction information contained in the output signals is missed due to compression. An MISR having m output terminals typically has a missing ratio of about 1/(2m).
An exemplary method for testing the CUT with the use of a reduced number of terminals is to provide latch circuits and shift resistors on opposite ends of the input and output terminals of the CUT for holding the logic states of the input signals and the output signals. In this case, the reduction of the numbers of the input terminals and the output terminals is achieved by serial/parallel conversion. Where the shift resistors each have m stages, for example, the tester should apply the input test pattern at a speed m times the operation speed of the CUT.
FIG. 19 is a block diagram for explaining an example of the conventional method for reducing the number of the input terminals. This method is intended to reduce the number of the terminals by grouping input terminals having the same logic state (see, for example, K. Chakrabarty, B. T. Murray, J. Liu and M. Zhu, “Test Width Compression for Built-in Self Testing”, Proceedings International Test Conference, IEEE Computer Society, p.328–337, 1997). In this method, an output (input test pattern) from a test pattern generator 50 constituted by two-bit counters is efficiently inputted to input terminals X1 to X5 of a CUT 52 through a connection expansion circuit 51. The input test pattern is intentionally expanded by adding logic state X (referred to as “don't care” state assuming either logic 1 or logic 0) to the input test pattern for higher sharability. The illustrated input terminals X1 to X5 herein assume the “don't care” state. In this method, however, it is impossible to cause the CUT 52 to operate in conformity with the original input test pattern, requiring processing of the test pattern. Since the test pattern generator 50 and the connection expansion circuit 51 are incorporated in an integrated circuit for the test, this method does not directly relate to the tester. That is, this method is not intended to use a test pattern prepared for the CUT 52, but efficiently use the pattern generator 50 utilizing the LFSRs and the counters. Therefore, terminal assignment for the reduction of the number of the terminals should be determined in consideration of the internal state of the CUT 50, making it difficult to realize a practical circuit.
FIG. 20 is a block diagram for explaining an example of the conventional method for reducing the number of the input and output terminals. This method is disclosed, for example, in Japanese Unexamined Patent Publication No. 10-132902 (1998). In this method, boundary cells 60 to 62 (bidirectional drive/receive IO cells 1 to L (BIDI1 to BIDIL) based on the JTAG joint test action group) standard specified by IEEE1149.1 are used. In a JTAG architecture, common IO lines 63 to 65 of the boundary cells 60 to 62 for serial connection are connected to a single IO line 66 for sub-grouping at a position indicated by a dotted reference line 67 for the reduction of the number of terminals connected to the outside. The boundary cells 60 to 62 are each connected to a data input line 68 to 70, a reception data line 71 to 73 and an HZ control line 74 to 76. In this method, it is merely possible to select one of the boundary cells 60 to 62. Even if two or more of the boundary cells 60 to 62 are simultaneously selected, a signal inputted from the common IO line 66 is transmitted through the common IO lines 63 to 65 to the reception data lines 71 to 73. Therefore, it is impossible to perform a test requiring different logic input signals. Where signals are transmitted from the inside to the outside, the boundary cells 60 to 62 cannot simultaneously be activated, so that the reduction of the number of the terminals is virtually failed. Where the boundary cells 60 to 62 are connected by the JTAG architecture, the signals can be set at any logic state by the serial input. However, the internal operation cannot be performed at a speed close to the actual speed, because time is required for the transfer of the internal data. In addition, the length of the test pattern is enormously increased, because the test pattern is serially inputted.
Further, the arts are disclosed in Japanese Unexamined Patent Publication No. 11-317671 (1999) and International Publication No. 98/43359 relate to methods for compressing test patterns, but not to the reduction of the number of the terminals of the tester.
However, the conventional testers and test methods have drawbacks such that: where the reduction of the number of the terminals is achieved by the compression of the outputs, the shipping quality is deteriorated with some errors; where the reduction of the number of necessary terminals is achieved by operating the tester at a high speed, the operation speed of the tester should be increased several times; and where the reduction of the number of the terminals is achieved by the application of the test pattern by means of the LFSRs and the like, the common line fixed for the reduction of the number of the terminals by sharing the terminals provides a reduced freedom, and the original test pattern cannot be reproduced with high fidelity by employing the test pattern uniquely provided by the LFSRs.